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Digital Logic Design Final Project
Jun 25, 2017
2 minutes read

The final design project for ECE 271 this year was to develop an intermediary driver for several possible inputs (8 pushbuttons, or a Nintendo 64 Controller) to map to several possible outputs (a NES or SNES console).

Top Block Diagram of our team’s project design.

This project involved quite a few long evenings, with lots of design work, planning, testing, programming and scripting. I was primarily involved with testing every SystemVerilog module through ModelSim. I managed to get ModelSim working natively on Linux by installing Altera’s (now Intel’s) Quartus package and using ModelSim from there.

Thankfully, our FPGA model was well supported on Linux for native development. Lattice Semiconductor’s Lattice Diamond software had a native RPM package, perfect for my Fedora workstation.

The Lattice Semiconductor Mach XO3LF FPGA.

Throughout this project I learned a bit about what it takes to get a full team to work several weeks through a design process, quite a lot about hardware simulation and test, and a fair amount about SystemVerilog itself, as I had quickly become responsible for writing the entire Nintendo 64 controller driver.

Source code for the N64 Console hardware module of the project.

It turns out the Nintendo 64 controller has a pretty interesting ‘protocol’, which is well documented online on plenty of university lab websites.

I haven’t had the time to hook it up to a real console to test (I unfortunately do not have a NES or SNES), I am pretty confident based off testing results that this project should function on real hardware as it does in ModelSim!

Simulation results in ModelSim for the top module of the project.

You can read our complete lab report here.


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